IMPLEMENTATION OF 16 BIT RISC PROCESSOR USING VHDL. (Global Journal of Advanced Engineering Technologies and Sciences, 2016)
Study over the years has shown that simple instruction are used most of the time in CISC ( Complex Instruction Set Computing ) processors and many complex instructions can be replaced by group of simple instructions. In that sense RISC (Reduced Instruction Set Computing) processor are designed to execute very few simple instructions. They operate on data which is mostly present in internal registers. Most of the RISC processors use hardwired control approach which simplifies design process. External memory is accessed by LOAD and STORE instructions. RISC processor supports only few addressing modes and most of them are register based. Pipelining is used to improve the throughput of the processor by dividing the instruction execution in stages. Although single instruction takes same time for execution as in sequential execution, parallel operations on instructions in different stages reduces the overall time of execution. The balance of work between different stages of pipelining is important as the slowest stage of the pipeline decides the throughput of the processor. The consequences of pipelining are the structural hazards, data hazards and control hazards. They can be handled using the methods of forwarding, stalling and flushing. Stalling degrades the performance by delaying the instruction execution. Prefetching unit is designed which works as a small cache. It is used to prefetch the instructions from memory and stored them inside the buffer. Developed RISC processor handles the hardware interrupts and exceptions. RESET has been assigned the highest priority. Six external hardware interrupts are available and are vectored. Overflow and undefined instruction exceptions are also dealt with. VHDL has been used for modeling the processor. Xilinx ISE 9.2i is used for simulation, synthesis and physical implementation. Hierarchical approach is used for modeling the RISC processor. Basic units are described using behavioral programming and they are interconnected using structural programming to form complete RISC processor..